With recent progress of technology relating to LSIs, a plurality of LSIs implementing sophisticated digital signal processing have been incorporated into mobile equipment. Since the mobile equipment typified by cellular phones is driven by batteries, reduction of power consumption in the incorporating equipment by shutting off power supply to an LSI which is not in operation has been widely performed for the purpose of extending the operating time thereof. To bring the LSI to an operating state again after the shut-off of the LSI, it is necessary to initialize (reset) the LSI appropriately. In particular, the reset at turning on of power is called power-on reset.
To appropriately generate a signal for this power-on reset, the use of a configuration in which a CR time constant circuit and an inverter are combined is known to date. Hereinafter, a conventional technique will be described with reference to FIG. 12. A circuit shown in FIG. 12 is configured to generate a power-on reset signal 1220 from an inverter 1210 constituted by a p-MOS transistor 1215 and an n-MOS transistor 1217 when a potential 1203 at a CR time constant circuit constituted by a resistor 1201 and a capacitance 1202 exceeds the threshold voltage of the inverter 1210.
In addition to the configuration shown in FIG. 12, a configuration including a voltage divider circuit constituted by a resistance, a comparator, a time-constant circuit constituted by, for example, a rated current generator and a capacitance, and an inverter is proposed as a power-on reset circuit in Japanese Laid-Open Publication No. 10-207580, for example.
(Problems to be Solved)
However, any of the conventional circuit configurations is formed by a resistor and a capacitor, so that the configurations are highly susceptible to characteristic errors in the process of fabricating a semiconductor circuit. Accordingly, the conventional circuit configuration shown in FIG. 12 has a problem that a period during which a reset signal is active changes from one product to another, and thus the reset is stopped before the power-supply potential at an LSI or a circuit block to be reset (hereinafter, collectively referred to as “a circuit block”) rises to an appropriate value.
The configuration proposed in the above publication is complicated, so that there arises a problem that the configuration cannot be incorporated into an LSI easily.